1. Technical Field
The present invention relates generally to communication link circuits, and more particularly, to communications link quality measurement circuits.
2. Description of the Related Art
Interfaces between present-day system devices and also between circuits have increased in operating frequency and complexity. In particular, high speed serial interfaces employ sophisticated clock-and-data-recovery (CDR) receiver techniques including data/clock extraction, jitter reduction via feed-forward and feedback circuits, phase correction, error correction, error recovery circuits and equalization circuits in order to improve performance.
Channel quality and bit error rate (BER) requirements of a given interface determine the “difficulty” of the interface in terms of receiver signal processing requirements and power/voltage requirements, transmitter power levels and overall interface architecture. Generally, especially in an integrated circuit (IC) implementation, a wide margin is provided to meet various customer and channel requirements, yielding a less than optimal design from a power/complexity design point. The above-incorporated patent applications describe techniques for adapting interface circuits in order to reduce complexity and power requirements. However, it is necessary to measure interface signal quality in order to adapt an interface dynamically to channel and application conditions. Even with statically selectable interface complexity and power/voltage levels, in order to know the confidence level of an interface, testing is required.
Measurements of interface quality are typically performed by phase margin measurements, e.g., a receiver eye diagram measurement that provides a measure of the performance of the interface on a given physical channel. Other techniques include measuring loop error parameters of a PLL (phase-lock-loop) or DLL (delay-locked loop) in order to determine the level of jitter present at the receiver.
However, the interface may not already include a DLL or PLL circuit adaptable for measuring loop error parameters as part of the design, and such circuits are costly additions to a system (e.g., such circuits have high area and power requirements) and are inherently mixed-signal circuits that are difficult to design and implement. Further, other measurement circuits such as eye diagram measurements are also costly to implement. The above techniques are also not always indicative of true channel quality, as depending on interface design, decrease in eye width or increase in PLL/DLL error signal amplitude may not accurately indicate the resulting channel quality.
It is therefore desirable to provide a method and apparatus for measuring interface quality that provides an accurate estimate of the difficulty of achieving a particular level of interface BER performance. It would further be desirable to provide a method and apparatus for measuring interface quality that have low incremental cost for addition to an integrated circuit having CDR receiver circuitry.